1. Field of the Invention
The subject matter of the present application relates to methods of thinning microelectronic or semiconductor elements such as semiconductor chips and wafers and methods of handling such elements.
2. Description of the Related Art
Microelectronic elements such as semiconductor chips commonly are provided with elements which protect the microelectronic element and facilitate its connection to other elements of a larger circuit. For example, a semiconductor chip typically is provided as a small, flat element having oppositely facing front and rear surfaces and contacts at the front surface. The contacts are electrically connected to the numerous electronic circuit elements formed integrally within the chip. Such a chip commonly is provided in a package having a miniature circuit panel referred to as a substrate. The chip is typically mounted to the substrate with the front or rear surface overlying a surface of the substrate, and the substrate typically has terminals at a surface of the substrate. The terminals are electrically connected to the contacts of the chip. The package typically also includes some form of covering overlying the chip on the side of the chip opposite from the substrate. The covering serves to protect the chip and, in some cases, the connections between the chip and the conductive elements of the substrate. Such a packaged chip can be mounted to a circuit panel such as a circuit board by connecting the terminals of the substrate to conductive elements such as contact pads on the larger circuit panel.
In some applications, it is desirable to form vertically stacked assemblies of microelectronic elements such as semiconductor chips. Such assemblies can be formed at wafer-level by stacking and electrically interconnecting two or more semiconductor wafers atop one another and then severing the semiconductor wafers into individual stacked assemblies each containing two or more corresponding stacked electrically interconnected semiconductor chips. A stacked assembly incorporating plural semiconductor chips saves space because it requires roughly the same amount of area of a circuit panel as an individual semiconductor chip of the stacked assembly. Such assembly may also achieve greater performance per cost and area requirements due to reduced interconnection lengths between semiconductor chips within the stacked assembly.
Often the thickness of a semiconductor wafer is reduced prior to assembling the semiconductor wafer with other semiconductor wafers such that the stacked assembly of semiconductor wafers has a smaller thickness than if the semiconductor wafers had not been processed in this way. Reducing the thickness of each semiconductor wafer also permits the vertical interconnects of each wafer to extend only partly through the original thickness of the semiconductor wafer, lowering the cost of forming the vertical interconnects.
Despite the considerable effort devoted in the art to development of methods of stacking and processing semiconductor wafers, further improvement would be desirable.